CPLD/FPGA Design Tools Buyer’s Guide
As programmable logic devices play an ever greater role in
communications equipment and as gate-counts grow exponentially, the need for powerful design tools follows. Both logic device suppliers and EDA vendors are responding to the challenge.
By Janine Sullivan
Designers of complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs) must wade through several layers of design before programming the actual device. These layers include design entry, simulation, place-and-route, timing analysis, simulation, and testing. Various design tools can be used in the early and latter stages, but for placing, routing, and timing analysis, programmers usually need to use vendor-specific software.
The market for CPLDs and FPGAs is growing for
numerous reasons. As time-to-market pressures continue to mount, the programmable option that has long been attractive for prototyping is now showing its advantages for finished goods. This programmable option trend is growing because programmable device complexity has increased, prices have fallen, devices are reprogrammable as upgrades occur, and ASIC manufacturers are typically not interested in low-volume jobs. Additionally, the actual design tools for the CPLDs and FPGAs are very inexpensive, with some
vendors offering them at no charge.
Kenn Perry, director of software marketing at Xilinx, reports that FPGAs represent the fastest growing logic market. Andy Robin, vice president of marketing at Vantis, points out that CPLDs are also a large programmable logic market, citing Dataquest figures for global market sizes of 1,100,000,000 FPGAs and 800,000,000 CPLDs in 1998.
What’s available
According to Rita Glover, president and senior analyst at EDA Today, L.C. (Phoenix, AZ), most CPLD
and FPGA designers were using generic electronic design automation (EDA) tools to design their front ends, but now many CPLD and FPGA vendors are offering entire design packages. Some device vendors are branding software products produced by the EDA houses. This doesn’t leave out the EDA vendors, however. Many EDA vendors are working closely with device manufacturers to streamline the design process, allowing device designers to simulate at the system level. Some EDA vendors are also offering
management packages that run vendor-specific place-and-route tools as add-ons.
All of the vendors in this buyer’s guide offer PC-based software, and most offer packages for workstations as well. I interviewed many of the CPLD and FPGA device vendors to get their views on key issues and trends for design tools. For a comprehensive listing of vendors and their design tools, see the product table on pages 47–52.
The design process
A designer’s first step is to understand the nature of
the design logic and decide whether a CPLD or an FPGA is needed. A CPLD offers a product term-based architecture (the interconnect structure is fixed). This leads to guaranteed timing delays across the device. Good applications for CPLDs include low-density, high-speed random logic applications such as control logic. Constructed of an array of logic blocks, an FPGA offers a more flexible interconnect architecture with a programmable interconnect structure. Good applications for FPGAs include system paths,
data paths, and digital signal processing.
Designers can choose a device vendor and a design entry scheme, once a device is selected. A schematic-based approach is good for low-density designs, while a behavioral/ text-based approach using languages such as Verilog or VHDL is useful for more complex designs.
Next, the design is entered into vendor and device specific place-and-route software to analyze timing. Once the design is optimized, it’s time to generate a bit stream and program the
actual device. If designers work with EDA tools, they can simulate their device at the system level before programming.
Choosing a CPLD
“First, determine what your design needs are and then pick the family that will best suit your needs,” advises Chris Schell, product marketing manager for the programmable logic business line at Philips Semiconductors. If several device families seem to suit a design, Schell advises talking to the technical support and sales staffs to find out about
additional benefits and design tools. The programmable logic vendor should ask what kinds of design tools the designer is currently using and what sort of design entry needs to be done. “Based on the answers to these questions, the customer should choose the vendor that has the best devices, tools, and support,” remarks Schell.
Philips offers CPLDs that span from 32 to 960 macrocells and are supported by the XPLA Professional and XPLA XL proprietary design tools. The company’s devices are
also supported through EDA vendors including Viewlogic, Synopsys, Exemplar, Synplicity, OrCAD, Cadence, and Mentor.
Both proprietary design tools include functional and AC timing simulation, power consumption estimation, device fitting, and VHDL and Verilog timing models for use in third-party simulators. XPLA Pro supports schematic, Verilog, and Philips HDL (PHDL) design entry, while XPLA XL only supports PHDL entry. Either package will accept electronic design interchange format (EDIF) flows from
third-party tools. The company provides free reference designs, such as a PCI target design. PCI and I
2
C seem to be the most requested designs.
CPLDs are generally well-suited for use in control logic. Andy Robin, from Vantis, explains, “Unless your design has very slow control logic, you should use a CPLD because CPLDs offer immediate functionality when powered up.” FPGAs need to reconfigure their logic pattern when turned off and then turned on again. While an FPGA may only take up
to one minute to configure, in many systems, the control logic needs to function as part of the power-up process.
Vantis offers back-end implementation tools for CPLD design, including DesignDirect Base software, which has been shipping since January, and DesignDirect Vista, which offers OEM VHDL/Verilog synthesis capabilities from Exemplar Logic and simulation capabilities from Model Technology. DesignDirect Base software includes the Performance Analyst feature, a static timing analysis tool with
interactive search and query capability that helps the designer rapidly identify performance bottlenecks. Reference designs for the CPLDs are free on the company’s Web site.
Choosing a CPLD vendor may take some time. Dave Greenfield, director of technical marketing at Altera suggests, “designers (should) find a supplier with a complete package of solutions that will address all of their needs. It is also important to find a supplier that drives innovation in silicon as well as design tools.”
To meet this challenge, Altera offers both EEPROM (product term) CPLDs and SRAM (see table) CPLDs. The company’s MAX+PLUS II software package is a design system that interfaces with EDA packages, such as synthesis tools from Synopsys or Synplicity and simulation tools from Model Technology or Cadence. Altera works with forty different partner companies to ensure smooth interfaces.
A single graphical user interface (GUI) drives all portions of the software, supporting schematic, VHDL,
Verilog, and analog HDL (AHDL) designs. Altera offers intellectual property (IP) blocks with a choice between OpenCore, which enables customers to download and test functions before licensing, and MegaWizards, which enables customers to make modifications to parameters such as bus width and latency, without getting into the IP.
One of the benefits of programmable logic devices is their ability to be reprogrammed as designs change. To this end, Lattice Semiconductor Corp. invented in-system programmable (ISP)
logic devices and now manufactures high-density ISP CPLDs. “ISP devices can be programmed and reprogrammed directly on the printed circuit board, drastically reducing design time, inventory and manufacturing costs, and time-to-market,” reports Daniel R. Zenka, public relations manager at Lattice.
To support its devices, Lattice supplies seven different design tool packages for PC and UNIX platforms, offering gate-level, VHDL, and Verilog design verification methods. Software capabilities
include timing driven synthesis, automatic error detection, design rule checking, flow management, static timing analysis, access to third-party CAE design libraries, and simulation. Lattice offers more than 400 software macros for its CPLDs that range in complexity from simple gates to adders, counters, and multipliers.
Choosing an FPGA
An important consideration in the design of increasingly complex FPGAs is the availability of cores. Most FPGA vendors offer cores and many CPLD vendors offer
IP blocks to speed design of common functions. Lucent Technologies’ microelectronics FPGA group,
for instance, directly licenses cores for PCI local bus interface implementation. The group also works with independent third-party IP vendors who develop cores for the company’s ORCA FPGAs and field-programmable system chips (FPSCs), devices that combine a standard cell embedded core and FPGA logic on the same chip. These cores range in function from ATM and other networking cores to DSP and
embedded microprocessor cores.
Carl Blesch, media relations manager at Lucent, explains why core usage is growing in popularity: “With today’s large FPGAs and FPSCs, entire systems are being placed on a single device. In order to get products to market, portions of designs must be reused — that’s where cores come in. They are reusable, fully functional design blocks.”
For Lucent’s FPGAs, popular schematic, synthesis, and simulation tools from EDA companies can be used for
design entry and verification. Lucent supplies the ORCA Foundry Development System for place-and-route, and the ORCA Foundry Designer series, which integrates tools from Viewlogic, Synopsys, and Lucent for a complete front-to-back design system.
QuickLogic is taking a slightly different approach from most vendors to IP. In addition to FPGAs, the company offers embedded standard products (ESPs), in which blocks of IP are implemented as hard functions (surrounded by user-configurable logic) that can be
customized. Rufino T. Olay III, QuickLogic’s development tools product marketing representative, explains, “This approach eliminates the problems inherent in soft IP while still providing a path for system designers to regain the short development times offered by standard products.”
To support its devices, QuickLogic offers development tools from an entry-level development environment to a complete front-to-back design solution. Operating on PCs or workstations, the tools are also
compatible with those from EDA vendors such as Synopsys, Viewlogic, Mentor Graphics, Synplicity, Exemplar, Synario, Aldec, and Simucad.
QuickLogic’s QuickWorks suite includes design entry, logic synthesis, place-and-route, timing analysis, and simulation. QuickTools-PC Plus is the company’s integrated entry-level FPGA development environment. The product includes schematic design entry through an extensive set of proprietary macrofunctions, place-and-route, static timing analysis, and interfaces
to third-party EDA environments. QuickTools for Workstations is an integrated FPGA development environment for Sun and Hewlett-Packard workstations, while QuickChip is an FPGA development software that works with third-party EDA tools.
Having invented the FPGA, Xilinx currently supports FPGAs up to 1,000,000 gates and has a two-tiered approach to IP. Kenn Perry asserts, “Cores are essential in a high-density solution.” The company provides its own cores, such as bus interfaces and DSPs, and
encourages access to third-party vendors who develop cores specifically for use with Xilinx devices through its Alliance Cores program.
Atmel Corporation has been in the programmable logic business for about eight years and, according to Joel Rosenberg, the FPGA product line director, the company offers many cores for its FPGAs, including PCI, fast Fourier transform (FFT), FIR filters, universal asynchronous receiver transmitters (UARTs), edge detection, convolver, signal pattern detector, pixel
average, and data encryption/decryption capabilities.
Atmel’s FPGA Designer package includes a design entry tool (HDL Planner) which supports VHDL (or Verilog), a synthesizer tool (Everest) for use with Atmel devices, and a place-and-route and timing analyst (Figaro). The software interfaces with numerous other vendor products, including those from Viewlogic, Exemplar, OrCAD, Synario, Synplicity, Synopsys, and Model Technologies.
The inexpensive nature of vendor software is making programmable
logic affordable to designers. Atmel has always offered its own design compilers for its FPGAs and CPLDs, and the company’s software is available free for qualified users on its Web site, www.atmel.com/fpgasw.html. Many other device vendors, such as Altera and Lucent, also offer free software on their Web sites.
Software integration
Many programmable logic vendors recognize the importance of integrating their design tools with other software packages, particularly those offered by
third-party EDA vendors. Many device designers already have CAD packages and prefer to continue working with the software they already know. For instance, the Designer series from Lucent utilizes IntelliFlow from Viewlogic for design, flow, and project management. The company also provides the ORCA Foundry Control Center package for design, flow, and project management with the Foundry design environment.
Xilinx, manufacturer of both CPLDs and FPGAs, recognized the importance of offering a software
package that integrates with the EDA vendors. The company has developed its Alliance software series, which runs on Windows PCs and UNIX workstations and allows integration into existing EDA environments such as Viewlogic and Mentor Graphics. It also offers capture and implementation (taking the logic and implementing it into the silicon) capabilities.
The company also offers its Foundation series, which runs on Windows PCs and offers packages that include design; languages such as schematic capture VHDL,
Verilog, and advanced Boolean equation language (ABEL); place-and-route; simulation; and synthesis capabilities. The company currently has an installed base of 50,000 to 60,000 software seats and regularly issues updates to customers.
EDA vendors
Numerous EDA vendors support the growing CPLD and FPGA market. Most are working closely with device houses to allow seamless integration between the vendor’s place-and-route tools and the EDA house’s larger system design/simulation
package.
To support the programmable logic market, OrCAD has developed OrCAD Express, which works with the company’s Capture (or Capture CIS) environments to design and simulate PLDs and FPGAs up to 100,000 gates. Running on Windows-compatible platforms, the software features a VHDL editor/debugger, logic synthesis, and gate-level and timing simulation. It also features macro libraries and simulation models for industry-standard devices, as well as specific devices from Actel, Altera, Lattice, Lucent,
Philips, Vantis, and Xilinx. The software offers multichip and system simulation.
The software can also be used to design programmable ROMs and ASICs. Using industry standards for data interchange, the software allows interfacing with other tools, such as those from Cadence, Mentor, and Model Technologies.
For CPLD and FPGA systems design, Viewlogic offers a complete front-end solution that performs all functions except place-and-route. It consists of a schematic capture tool (ViewDraw); a
VHDL/Verilog synthesis tool (FPGA Express); and VHDL, Verilog, and gate-level cosimulation (The Fusion family of simulators includes Fusion/SpeedWave, Fusion/ VCS Express, and Fusion/ViewSim, respectively). The entire suite can be managed by the IntelliFlow package, a complimentary add-on package that acts as a CPLD and FPGA flow manager, integrating all of the Viewlogic tools and vendor place-and-route tools under one GUI. After running the vendor-specific place-and-route tool, IntelliFlow brings the netlist
back into the Viewlogic environment in order to perform simulation. The Viewlogic tools can be used for board- or system-level design as well.
Viewlogic works with many CPLD and FPGA vendors, including Lattice, Lucent, Xilinx, Actel, Vantis, Atmel, Altera, Cypress, Philips, and QuickLogic, to ensure smooth interfaces.
What’s next
Vendors agree that the future of CPLD and FPGA design tools is excitng. Many vendors feel that software pricing will come down even more, and it will
become easier to integrate device manufacturer software with EDA software.
As silicon devices grow in complexity, the software will be challenged to keep up the pace. Vantis, for instance, is planning to move into the FPGA market soon with its new variable-grain-architecture FPGAs, which will be available with a later release of its DesignDirect software.
Increasing complexity for these devices and their design tools is a key issue. Chris Schell (Philips) suspects that “the next big challenge
will be the CAE tools for systems-on-a-chip (SOCs).” Carl Blesch (Lucent) also predicts that mixed ASIC-FPGA designs may be used for field-programmable SOCs, further challenging available design tools.
In response to the growing number of gates in FPGAs, many vendors recognize that it is time to move to team-based design. Ken Perry (Xilinx) observes, “As devices continue to get bigger, one designer cannot comprehend and/or manage a 1,000,000-gate design. Design tools will need to handle the
concept of a workgroup (if they don’t already), have the capability to distribute processes across multiple users, and then bring them back together into one bit stream.”
Current developments at Xilinx include team-based design capabilities, with the next software generation of its Internet team-based design software scheduled for release this summer. Recognizing the importance of workgroups, Altera is releasing Quartus, a software package that supports higher-density designs (above 250,000
gates) and workgroup-based design, during the second quarter of this year.
Dave Greenfield (Altera) observes that another pressing need for design tools is to “address changes in verification. With devices reaching a higher number of gates, customers are spending 50% to 70% of design time in verification. This issue needs to be addressed in order to improve productivity.” Since one of the key benefits of a programmable logic device is improved time-to-market, this may be a significant issue for
the next generation of design tools.
Janine Sullivan is the president of The Write Solution based in Parsippany, NJ. She was formerly the chief editor for
Communications Products
magazine. She holds a BA from
the University of Delaware and an MA from Duquense University. She can be contacted at
write@planet.net
.
The author would like to thank Rita Glover, president and senior analyst at EDA Today, L.C., and Joel Rosenberg, FPGA product
line director at Atmel Corp., for their input and observations on industry issues.
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