Company/
Product
|
Description
|
Function
|
Output
|
Devices
supported
|
Actel Corp.
The Actel Desktop
|
Integrated FPGA and
simulation environment
|
Design entry, simulation, synthesis,
place-and-route, system verification, and device programming
|
VHDL
|
Actel
|
Aldec, Inc
Active-HDL
|
Integrated design and
simulation environment
|
A Windows-based design environment
for all stages of development, from HDL design entry to source-code debugging
|
VHDL
|
Supports all CPLD
and FPGA vendors
|
Altera Corp
MAX+PLUS
|
Integrated design
environment
|
Design entry, compilation, verification,
and programming options
|
VHDL,
Verilog,
AHDL
|
CPLD/FPGA
|
| Quartus
|
Integrated design
environment
|
Shortened compilation times with
incrementation compiler, improved
verification flow and SignalTap logic
analysis, NativeLink integration with
major design tools, and error location
and timing optimization capability
|
VHDL,
Verilog
|
Altera
|
Atmel Corp.
FPGA Designer 6.0
|
AT40K and AAT6K Series
FPGA Design suite
|
Multichip partitioning, automatic
place-and-route, floor planning, automatic macro generators and RAM compilers, static timing analysis, synthesis compiler
and bit stream generator
|
VHDL,
verliog
|
Atmel
|
Cadence Design
Systems, Inc.
Concept HDL System
|
Schematic and mixed HDL top-down and top-up design tool
|
Captures FPGA and PCB
logic in schematic, Verilog or VHDL form to drive synthesis through the Cadence Verilog XL, Affima NC, and third-party simulators
|
VHDL
Verilog
|
CPLD/FPGA
|
Cypress
Semiconductor
Warp Software
|
Programmable logic
design tool
suite
|
VHDL, Verilog, and a graphical finite state
machine editor for design entry; performs synthesis, fitting, and simulation
|
VHDL
Verilog
|
CPLD/FPGA
|
| ISR Software
|
In-system reprogrammable
software for CPLDs
|
Converts JEDEC files into Jam files used to
program in-system reprogrammable (ISR) CPLDs
|
Jam files
|
All Cypress ISR CPLDs
|
DynaChip Corp.
Dyna Tool
|
Integrated FPGA
development system; place-and route tool suite
|
Interfaces with front-end tools such as logic simulators and synthesis tools; performs place-and-route for FPGA and extracts post-route timing
|
VHDL
Verilog
|
DynaChip
|
Elanix, Inc.
SystemView
|
DSP/communications
system simulation
and analysis
|
Designs, simulates, and analyzes analog,
digital, mixed-mode communications, and DSP systems; interfaces to Xilinx CoreGEN to provide an implementation path into Xilinx FPGA hardware
|
VHDL or schematic
symbol output
|
Xilinx
|
Escalade Corp.
DesignBook
|
Integrated high-level
design environment
|
Accelerates testbench construction, complex
controller design, IP management, and reuse
|
VHDL
Verilog
|
Actel, Altera, Xilinx
|
Exemplar Logic
LeonardoSpectrum
|
HDL Capture, Synthesis,
verification, and place-and-route suite
|
Design entry, synthesis, analysis, Verification,
and place-and-route
|
VHDL, Verilog
EDIF, SDF
|
Actel, Altera, Atmel, Cypress, DynaChip, Gatefield, Lattice, Lucent, Philips, QuickLogic, Vantis, Xilinx
|
| LeonardoInsight
|
Debugging and analysis
of HDL designs with 5-way cross-referencing
|
Allows designers to perform cross-probing
between multiple
design views; each optimized view provides specific debugging or analysis information about a design.
|
VHDL, Verilog,
EDIF, SDF
|
Same as above
|
HP EEsof
HP DSP Designer
|
Schematic entry,
behavioral simulation, and behavioral synthesis
|
Performs optimization for area and
performance and generates HDL automatically for specific devices
|
VHDL
Verilog
|
Altera, Xilinx, and
customizable for others
|
Lattice Semi-
conductor Corp.
ispEXPERT Compiler
|
Tool suite
|
Operates in all leading third-party environments
for high-level Verilog and VHDL synthesis and design; provides optimization, mapping, place-and-route, debugging, and timing analysis, supporting all place-and-route, debugging, and timing analysis, support
|
EDIF, Verilog,
VHDL, SDF, JEDEC
|
Lattice
|
| ispEXPERT System with Synplicity
|
Tool suite
|
Synthesis, design entry, optimization, mapping,
place-and-route, debugging, timing analysis, and functional and timing simulation; Verilog and VHDL synthesis, ABEL and schematic entry, and third-party interfaces through EDIF support
|
EDIF, VHDL,
Verilog, SDF, JEDEC
|
Lattice
|
| ispEXPERT Compiler
with Viewlogic
|
Tool suite
|
Synthesis, design entry, optimization, mapping,
place-and-route,Synthesis, design entry, optimization, mapping,
place-and-route, debugging, timing analysis, functional and timing simulation, optional VHDL behavioral simulation
|
EDIF, VHDL,
Verilog, SDF, JEDEC
|
Lattice
|
| ispEXPERT System
Starter
|
Tool suite
|
Design
entry, optimization, mapping,
place-and-route, debugging, timing analysis, and functional simulation; schematic, ABEL entry and third-party interfaces through EDIF support
|
EDIF, VHDL,
Verilog, SDF, JEDEC
|
Lattice
|
Lucent
Technologies
Orca Foundry
Designer Series
|
Tool suite
|
Viewlogic's ViewDraw, ViewSim, SpeedWave,
Synopsys FPGA Express, Intelliflow, ORCA Foundry Development System
|
VHDL
Verilog
|
Lucent ORCA FPGAs
(supports all design sizes)
|
| Orca Foundry
Development System
|
Tool suite
|
Complete VHDL and Verilog HDL libraries for
ORCA, SCUBA macro-cell compiler, Trace Static Timing Analysis tool, timing-driven place-and-route tools, EPIC interactive design editor
|
VHDL
Verilog
|
Lucent ORCA FPGAs
(supports all design sizes)
|
Mentor Graphics
Corp.
Renoir
|
HDL graphical design
environment for FPGA and ASIC designers
|
Provides a graphical design environment that
generates Verilog and VHDL from a variety of diagram types such as block diagrams and state machines
|
VHDL
Verilog
|
(not device-specific)
|
| Packaged Power
|
HDL design flow for
FPGA and Desktop ASICs
|
Provides HDL design flow for FPGA and desktop
ASIC designs, including graphical design, management/capture simulation, synthesis, and synthesized netlists
|
Input language
neutral, VHDL or Verilog; output includes simulation results
|
CPLD/FPGA
|
Model Technology
ModelSim PE/VHDL
|
VHDL digital simulation
|
Behavioral, RTL, and gate-level
simulation of
VHDL designs; integrated source-code debugging and verification
|
Simulation results
(wave-forms, value dumps, and value lists)
|
All vendors who provide
VHDL libraries
|
| ModelSim PE/VLOG
|
Verilog digital simulation
|
Behavioral, RTL, and gate-level simulation of
Verilog designs; integrated source-code debugging and verification
|
Simulation results
|
All vendors who provide
VHDL libraries
|
| ModelSim PE/Plus
|
Mixed-HDL (VHDL and
Verilog) digital simulation
|
Behavioral, RTL, and gate-level simulation;
integrated debugging and verification
|
Simulation results
|
All vendors who provide VHDL or
Verilog libraries
|
OrCAD
OrCAD Express
|
Tool suite; adds VHDL-
based simulation and FPGA design to OrCAD Capture
|
Complete programmable logic design and
simulation system, integrating VHDL editor/debugger, logic synthesis, and gate-level and timing simulation
|
OrCAD schematic
to VDHL or Verilog model; EDIF and XNF netlists; JEDEC and HEX programming files
|
Actel, Altera, Atmel,
Lattice Lucent, Philips Vantis, Xilinx
|
| OrCAD Express Plus
|
Tool suite: advanced
edition includes timing-driven synthesis and large FPGA support
|
Complete programmable logic design and simulation system, integrating VHDL editor/debugger, sophisticated logic synthesis (powered
by Exemplar Logic) and gate-level and timing FPGA-specific and HEX programming files
|
OrCAD schematic to VHDL or Verilog models; EDIF and XNF netlists;and HEX programming files
|
Actel, Altera, Atmel,
Lattice Lucent, Philips Vantis, Xilinx
|
Philips
Semiconductors
XPLA Professional
|
Tool suite for design and
simulation with Philips CoolRunner CPLDs;design entry for targeting
|
Schematic, Verilog, and PHDL (Boolean equation)
design entry; provides both functional and timing simulation and dynamic current consumption estimation
|
JEDEC file for use in programming the device;VHDL and Verilog timing models are generated
|
Philips CoolRunner CPLDs including XPLA, XPLA Enchanced, and XPLA2 device families
|
| XPLA XL
|
Tool suite for design and
simulation with Philips CoolRunner CPLDs
|
PHDL (Boolean equation) design entry and
back-end fitting through EDIF flows from third-party
tools (OrCAD, Viewlogic, Synopsys, Synplicity, Exemplar); provides both functional and timing simulation and dynamic current consumption estimation
|
JEDEC; timing, fitter, and optimized equation reports; VHDL Verilog timing models are generated
|
Philips
|
QuickLogic Corp.
QuickWorks
|
ESP/FPGA tool suite
|
VHDL, Verilog, schematic and mixed-mode design entry, HDL synthesis, automatic place-and-route, Verilog/VHDL simulation
|
VHDL, Verilog
|
QuickLogic
|
| QuickTools Plus
|
ESP/FPGA tool suite
|
Schematic design entry, place-and-route,
timing analysis, and programming
|
VHDL, Verilog
|
QuickLogic
|
| QuickChip
|
ESP/FPGA design software
|
EDIF interfaces, place-and-route,
and timing analysis
|
VHDL, Verilog
|
QuickLogic
|
| QuickTools for
Workstations
|
ESP/FPGA design software
|
EDIF interfaces, place-and-route,
and timing analysis
|
VHDL, Verilog
|
QuickLogic
|
SynaptiCAD, Inc.
VeriLogger Pro
|
Integrated FPGA design
|
Verilog and timing simulation,
accepts
inputs from HP Logic
|
Verilog models
|
Actel, Altera, AMD,
Lattice, Lucent, Xilinx, and others
|
| WaveFormer Pro
|
RTL simulator and
Stimulus generator
|
Determines what is happening
on the internal
nodes of FPGAs that can't be directly probed by using WaveFormer Pro's RTL simulator with HP logic analyzer data
|
VHDL and Verilog
Stimulus Vectors from HP Logic
|
Actel, Altera, AMD,
Lattice, Lucent, Xilinx, and others
|
Synplicity, Inc.
Synplify
|
VHDL and Verilog synthesis
for FPGAs and CPLDs
|
Takes a Verilog or VHDL description of a design
and outputs a netlist ready for place-and-route using FPGA vendor tools
|
Netlist (EDIF, XNF,
etc); for place-and-route and post synthesis Verilog orVHDL simulation
|
Actel, Altera, Atmel,
DynaChip, Lattice, Lucent,
Philips, QuickLogic, Vantis,Xilinx
|
| HDL Analyst
|
HDL code analysis and
debugging environment
|
Creates a technology-independent RTL schematic
and a technology- specific gate-level schematic from Verilog or VHDL, and allows cross-probing back to source
|
Schematic display of
critical paths and timing information
|
Same as above
|
Synopsys, Inc.
FPGA Compiler II
|
High-end FPGA/CPLD
synthesis tool with ASIC-compatible design flows
|
FPGA/CPLD synthesis; includes support for
Design
Compiler scripting, .db output, and DesignWare components; for UNIX and NT platforms
|
VHDL, Verilog, EDIF, .db
|
Actel, Altera, Atmel,
Cypress, Gatefield, DynaChip, Lattice, Lucent, QuickLogic, Triscend, Vantis, Xilinx
|
| FPGA Express
|
Entry-level
FPGA/CPLD
synthesis tool with a range of design flows
|
Provides a range of design flows, constraint-entry,
timing analysis, and graphical tools for FPGA/CPLD synthesis; for Windows NT/98 platforms
|
VHDL, Verilog, EDIF, .db
|
Same as above
|
Vantis
DesignDirect
|
Tool suite
|
Schematic and ABEL design entry, functional
simulation, static timing analysis, CAE netlist support; Exemplar Logic synthesis and Model Technology simulation
|
JEDEC
|
Vantis
|
VeriBest, Inc.
FPGA Desktop
|
FPGA tool suite with full design
data management
|
Design environment with design and testbench
capture, design management, flow management, HDL simulation, HDL synthesis, and integration with FPGA vendor place-and-route software
|
VHDL, Verilog, EDIF, and
FPGA vendor-specific
formats
|
Actel, Altera, Lattice,
Lucent, ORCA, Xilinx
|
| VB DesignView
|
HDL and schematic design
data management
|
Design and data management support providing
virtual root management, configuration management, and implementation viewpoints; data management
integration with FPGA vendor tools
|
VHDL, Verilog
|
Actel, Altera,
Lucent, ORCA, Xilinx
|
| VB VHDL Simulation
|
VHDL simulation with
graphical stimulus generation
|
VHDL simulation
environment with source-level
debugging, hierarchy browser, and waveform display; run-time C-language interface and integration with Synopsys LMG SmartModels and Hardware Modeler
|
VHDL
|
Actel, Altera, Lattice,
Lucent, Xilinx
|
| VB FPGA Synthesis
|
FPGA synthesis
|
FPGA synthesis with support for vendor macros; user selectable FSM encoding and speed/area optimization; push-button flows and TCL/tk scripting support; timing constraints and graphical results viewing
|
VHDL, Verilog
|
Actel, Altera, Lattice,
Lucent, ORCA, Xilinx
|
| VB HDL Writer
|
Context-sensitive HD editor
|
Context-sensitive HDL text editor; color-keyed HDL
syntax; macros and templates for automatic code generation and expansion; integration with simulators allows HDL compilation from within the editor
|
VHDL, Verilog
|
Actel, Altera, Lattice,
Lucent, ORCA, Xilinx
|
|
VB Graphical HDL and
Design Capture
|
Design creation tools
|
Schematic capture, state-machine, flow-chart, and
truth table design creation tools integrated into one environment
|
VHDL, Verilog
|
Actel, Altera, Lattice,
Lucent, ORCA, Xilinx
|
Viewlogic Systems
FPGA Express
|
FPGA synthesis
|
Synthesis and optimization of any mix of VHDL,
Verilog, and EDIF source from a graphic interface or TCL scripting
|
Vendor-specific EDIF or
XNF netlist and timing constraint file
|
Actel, Altera, Atmel,
Cypress, DynaChip, Lattice, Lucent, QuickLogic, Trescend, Vantis, Xilinx
|
| IntelliFlow
|
Automated FPGA design process manager
|
Runs the entire FPGA
design process from one
graphical interface, design entry, simulation, synthesis, and place-and-route
|
Bit files for programming
FPGA or CPLD-
|
Actel, Altera, Lattice,
Lucent, Xilinx
|
WSI
PSDsoft 5.0
|
EDA tool suite
|
AHDL-based logic design, logic reduction and fitting,
MCU interface configuration, configuration of programmable functions (such as timer/counters and supervisory), Verilog full-chip simulation, memory mapping, and device programming
|
Verilog for chip simulation;
Intel Hex device map for programming; (Motorola-S ormat also supported)
|
WSI
|
Xilinx Inc.
Alliance series
|
Tool suite for integration
with EDA vendors
|
HDL design, mixed schematic capture with HDL, and
mixed EDA vendor design techniques; includes graphical constraints implementation, incremental design, and core integration editor, floor planner, minimum timing reporting,
timing-driven
|
VHDL, Verilog
|
Xilinx
|
| Foundation series
|
Tool suite for complete
HDL solutions
|
Fully-integrated design environment allowing access
to design entry, synthesis, simulations,
and implementation tools
|
VHDL, Verilog
|
Xilinx
|
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